1. Technical Field
The embodiments herein generally relate to electrical circuits and systems, and, more particularly, to systems and methods for implementing DC offset cancellation in cascaded amplifiers.
2. Description of the Related Art
A typical front-end analog transceiver is composed of several gain and filter stages. The total gain can be well in excess of 60 dB. FIG. 1 shows a set of differential amplifiers 100 connected in a cascaded configuration (101-103). Due to random mismatches in electronic devices, such as metal oxide semiconductor (MOS) devices a parasitic DC offset can exist between the differential inputs of the first amplifier stage 101. A DC input offset error as high as 1 mV is not uncommon. With a cascaded gain of 60 dB, this would translate into 1V differential output, which is typically higher than the supply voltage. This would significantly reduce the dynamic range of the transceiver. Clearly a method of calibrating the DC offset error is required.
There are several DC offset error correction mechanisms discussed in the literature. DC offset cancellation strategies fall in one of two categories. In continuous DC offset 204 cancellation (as shown in FIG. 2), an AM loop around each amplifier is continuously running that measures the DC offset and adds/subtracts current and/or voltage by some active device to cancel the measured DC offset. Unfortunately, this method generally has several disadvantages. First, the loop continuously running is contributing to noise at the output of the amplifier 201, which is especially problematic for front-end amplifiers. Spurs can also be generated by the DC offset cancellation loop 200 by hard switching blocks such as comparators 202. Second, the closed loop response of the DC offset cancellation loop may interfere with the main amplifier, causing instability. Although this can be mitigated by ensuring that the DC offset loop bandwidth is much smaller than the main amplifier, this can be a difficult task for a cascade of amplifiers or it may necessitate large filters 203 necessary to lower the loop bandwidth. Third, since the DC offset cancellation loop 200 is always on, it may incur significant DC power consumption.
The other method of canceling DC offsets is by a digitally controlled loop 300, shown in FIG. 3. This is accomplished by having a digital control loop sweep through discrete DC steps (302-304) and determining which setting yields the minimum DC offset error. A digitally controlled loop 300 does not have the disadvantages of its analog counterpart, but it has its own shortcomings. First, since the DC cancellation loop is digital, it introduces a lot of switching noise at the output of the amplifier 301. One solution to this problem is to turn off the digital calibration loop once the DC offset cancellation loop has settled. Second, for very fine control over DC offset, very tight matching of the DC step size is required. This can result in an impractically large area for the DC offset calibration circuitry 304. For example, if a cascade of amplifiers of 60 dB is used and DC calibration is required, this would necessitate the use of fine DC steps sizes with 10-bit resolution (6 dB per bit). Accordingly, there remains a need for a digital DC offset error correction technique with high precision, especially in the context of a cascade of amplifiers.